1. Field of the Invention
The present invention relates, in general, to integrated circuits and, more particularly, to sense amplifiers in integrated circuit memory devices.
2. Relevant Background
Semiconductor memory devices include sense amplifiers to sense weak signal levels from storage capacitors and amplify those weak signals to levels sufficient to drive other circuitry. Similar devices are used in other integrated circuit devices that sense, hold, and amplify signal levels. In a typical dynamic random access memory (DRAM) circuit, a data bit is stored as charge in a storage capacitor. A number of these storage capacitors are served by a single sense amplifier. During reading, writing, and refresh operations appropriate addressing signals are applied to couple one of the capacitors through a bit line to a latch node of the sense amplifier. Before accessing one of the capacitors, the bit lines are equalized to a selected precharge voltage during a precharge operation. The selected precharge voltage is usually a voltage midway between logic high level and a logic low level.
When an address-selected capacitor is coupled to one of the bit lines feeding into a sense amplifier the charge stored in the capacitor alters the signal on the bit line moving it incrementally towards either a logic high or a logic low level. Because it is desirable to make the storage capacitor as small as possible, the bit line may only move a few hundred millivolts or less from the equalization level. The sense amplifier serves to amplify this small signal level to drive the bit line to either a logic high or logic low voltage level depending on the direction in which the bit line moved with respect to the equalization level.
Sense amplifiers typically comprise a latch circuit formed, for example, by a pair of cross-coupled high gain inverters. A typical latch circuit has two latch nodes that each serve as a differential input coupled to sense a signal on the bit line during sensing to drive the bit line to the logic levels. It is desirable that sense amplifiers accurately sense the bit line signal and quickly set the latch outputs. During read operations, each latch output is coupled to a data input/output (I/O) line by a pass transistor as soon as the latched output is available. To reduce access time, it is desirable to activate the pass transistor as soon as possible after the latch output is stable. Also, it is desirable to make the pass transistor relatively large to couple the latched signal to the data line quickly and with little signal loss. However, to use a large pass transistor the latch must be strong in order to hold the latched signal when coupled to the parasitic load presented by the data lines.
The latches within the sense amplifiers typically comprise P-channel field effect transistors (FETs) coupled to a positive power supply such as V.sub.DD by a P-channel FET driver switch, also referred to as a "high-side" driver. Similarly, N-channel FETs in the latches are coupled to a relatively negative power supply (such as V.sub.SS or ground) using an N-channel driver switch, also referred to as a "low-side" driver. For convenience, the latch power supply nodes are designated herein as an LN node (i.e., a node coupling the low-side driver switch to the N-channel FET devices within the latch) and an LP node (i.e., a node coupling the P-channel FET devices within the latch to the high-side driver switch).
In a standby or precharge mode the driver switches are turned off so that the latch lacks sufficient power to drive a signal on the latch output nodes. In this standby mode, the latch input nodes follow the signal to be sensed. To read data from the memory cell, the driver transistors are turned on thereby enabling the latch to amplify the sensed signal on the bit lines and drive the latch output nodes to appropriate logic levels.
In DRAM devices, for example, rapid driver turn-on can cause the sense amp to latch to an incorrect state due to the effects of capacitance and transistor imbalances within the sense amplifier. During overly rapid turn on, parasitic coupling through transistors in each sense amplifier may pull both differential latch nodes of the sense amplifier toward either a logic HIGH or logic LOW depending on whether lower drive transistors or upper drive transistors turned on first. Because one of the drive transistors is typically implemented using N-channel devices and the other using P-channel devices, it is common that the N-channel side will turn on first. To counter this problem the driver transistors are desirably activated slowly during initial sensing to allow the sense amplifier to accurately latch the bit line value. However, after initial sensing has begun, the sense amps are preferably turned on hard to quickly amplify the differential voltage on the latch nodes (i.e., the bit lines) to minimize access time. This type of sensing is referred to herein as "dual-speed" sensing.
In many DRAM designs, the LN and LP nodes are shared among a plurality of sense amplifiers. These designs allow the driver switches to be implemented with large, low impedance switches. By low impedance it is meant that they are low impedance with respect to the transistors in the latch itself including pass transistors that couple the latch output nodes to the data line. These strong driver switches ensure that the sense amplifiers can be turned on hard when necessary. Dual-speed sensing is provided by implementing the driver switch with two or more transistors of different size. For example, a small transistor having high on-resistance is activated first to provide the initial sensing. After a preselected delay, a larger transistor having low on-resistance is activated to turn the latch devices on hard.
However, shared drivers result in long LN and LP lines in large memory devices such as 64 M, 256 M, and larger memory arrays. Parasitic impedance in the long lines results in voltage drops or sagging when a high current flows in the LN and/or LP lines. An example case is illustrated by a group of sense amplifiers sharing LN and LP lines, in which only one sense amplifier at the end of long LN and LP line is trying to sense a "0" and all other sense amplifiers are sensing a "1". When the sense amplifiers are simultaneously activated, the large number of sense amplifiers that are sensing a logic "1" will disturb the voltage at distant locations on the LN line. A sense amplifier that is coupled to that portion of the LN line will take longer to sense a logic "0". Hence, the sense amplifier performance is sensitive to the pattern of 1's and 0's stored in the memory. To accommodate this pattern sensitivity, the DRAM must be operated using access timing that will allow the slowest sense amplifier to accurately sense and drive the stored value regardless of the pattern. It is desirable to minimize pattern sensitivity to improve cell access speed.
To minimize pattern sensitivity, each sense amplifier may be provided with its own local driver transistors. In a typical memory device the power supply busses are distributed throughout the chip area. Each sense amplifier can be coupled to a nearby power supply bus using short, low impedance interconnect through a local drive transistor. However, the local drive transistors must be significantly smaller than the shared drive transistors. These smaller drive transistors limit the sense amplifier's ability to drive the data I/O line. High switching current in the latch can destabilize the sense amplifier by allowing the LN and LP nodes to drift impermissibly far from the power supply bus voltages.
It is not practical to implement dual slop sensing using the dual transistor technique described above in a local drive transistor design because of the chip area consumed by two transistors required for each sense amplifier. Instead, dual speed sensing is provided with local drive switches by generating control signals to the driver transistors that settle temporarily at a level between a logic low (i.e., V.sub.SS) and a logic high (i.e., V.sub.DD). After a predetermined delay time, the control signals continue to the full logic levels to turn the driver transistors, and so the latch devices, on hard. This type of design is described in U.S. Pat. No. 5,334,890 titled "SENSE AMPLIFIER CLOCK DRIVER" issued Aug. 2, 1994 and incorporated herein by reference. This design distributes the driver transistors reducing pattern sensitivity. However, to provide sufficiently stable LN and LP nodes the control signals to the local drive transistors must have carefully controlled signal levels, timing, and slew. Hence, local driver designs require relatively complex control circuitry that increases the overall size overhead of the design to levels that may be inappropriate for some applications.
A need remains for a sense amplifier design and method for operating a sense amplifier that provides dual slope sensing and is compatible with large shared driver designs as well as local driver designs that offer pattern insensitivity. Moreover, a need exits for a high speed sense amplifier that can be implemented with simple, compact circuitry for high capacity memory designs.